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Wafer-Level Testing and Test During Burn-In for Integrated Circuits
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Wafer-Level Testing and Test During Burn-In for Integrated Circuits Hardcover - 2010 - 1st Edition

by Sudarshan Bahukudumbi; Krishnendu Chakrabarty


Details

  • Title Wafer-Level Testing and Test During Burn-In for Integrated Circuits
  • Author Sudarshan Bahukudumbi; Krishnendu Chakrabarty
  • Binding Hardcover
  • Edition number 1st
  • Edition 1
  • Pages 198
  • Volumes 1
  • Language ENG
  • Publisher Artech House Publishers
  • Date 2010
  • Illustrated Yes
  • Features Illustrated, Index, Table of Contents
  • ISBN 9781596939899 / 1596939893
  • Weight 0.95 lbs (0.43 kg)
  • Dimensions 9.1 x 6.2 x 0.7 in (23.11 x 15.75 x 1.78 cm)
  • Library of Congress subjects Integrated circuits - Testing, Semiconductors - Testing
  • Library of Congress Catalog Number 2010455090
  • Dewey Decimal Code 621.381

Media reviews

Citations

  • Scitech Book News, 06/01/2010, Page 162
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Wafer-Level Testing and Test During Burn-In for Integrated Circuits
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Wafer-Level Testing and Test During Burn-In for Integrated Circuits

by Sudarshan Bahukudumbi Krishnendu Chakrabarty

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Wafer-Level Testing and Test During Burn-In for Integrated Circuits (Artech House Integrated Microsystems) Illustrated Edition by Sudarshan Bahukudumbi (Author), Krishnendu Chakrabarty (Author)

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NEW: WAFER-LEVEL TESTING AND TEST DURING BURN-IN OF INTEGRATED CIRCUITS 2010 HC
Wafer-Level Testing and Test During Burn-In for Integrated Circuits (Artech House Integrated Microsystems) Illustrated Edition
by Sudarshan Bahukudumbi (Author), Krishnendu Chakrabarty (Author)
OUR REFERENCE: VLA-S9-B3-HC-1596939893-1-LB-2010-B8
DESCRIPTION
Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this book helps practitioners address the issue of enabling… Read More
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Wafer-Level Testing and Test During Burn-In for Integrated Circuits (Artech House Integrated...
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Wafer-Level Testing and Test During Burn-In for Integrated Circuits (Artech House Integrated Microsystems)

by Bahukudumbi, Sudarshan

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ISBN 10 / ISBN 13
9781596939899 / 1596939893
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hardcover. Good. Access codes and supplements are not guaranteed with used items. May be an ex-library book.
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